1. Field
Example embodiments relate to a method of manufacturing a transistor having metal silicide and a method of manufacturing a semiconductor device using the same. More particularly, example embodiments relate to a method of manufacturing a transistor including a gate having a stacked structure of polysilicon and metal silicide and a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
In an information society, in order to rapidly process relatively large amounts of data, highly integrated semiconductor devices having high data transmission speeds may be required. However, as the semiconductor devices become highly integrated, ensuring required characteristics of the semiconductor devices becomes more difficult.
For example, gate lengths and junction depths of sources/drains in the semiconductor devices are being reduced, thereby causing increases in the resistances of the gates and the source/drain regions. The increases in the resistances cause deterioration of the high speed operation of the semiconductor devices and cause undesirable power consumption.
In order to improve the problem, a method of forming a metal silicide layer including compounds of metal and silicon on the gate electrode and the source/drain region has been used. The metal silicide layer may include a tungsten silicide layer, a titanium silicide layer, a cobalt silicide layer and a nickel silicide layer. Among them, the nickel silicide layer may have a lower silicon consumption rate and a lower specific resistance. Also, the nickel silicide layer having a line width of less than 0.1 μm may maintain uniform surface resistance and the nickel silicide layer may be more easily formed at a relatively low temperature. Thus, nowadays, the nickel silicide layer may be actively employed in highly integrated semiconductor devices, e.g., a nano-CMOS transistor.
Generally, a gate electrode having the metal silicide layer may have a stacked structure of polysilicon and metal silicide. An insulation layer spacer may be provided on sidewalls of the gate electrode so as not to form the metal silicide on the sidewalls of the gate electrode. However, when the gate electrode having the metal silicide may be formed, a silicidation reaction may occur so rapidly that the metal silicide layer grows to the upper surface of the spacer at a lateral side of the gate electrode. In example embodiments, unnecessary metal silicide residue may be frequently formed on the upper surface of the spacer. Particularly, when the nickel silicide is used for the metal silicide, the metal silicide residue frequently occurs due to thermal instability of nickel silicide.
The metal silicide residue may be formed along the upper surface of the spacer, thereby causing a short failure between the gate electrode and a contact plug connected to the source/drain of the transistor. Further, when the contact plug is misaligned to be closely adjacent to the gate electrode, short failures between the gate electrode and the contact plug may occur more frequently.